PLDs are a well-known type of integrated circuit that may be programmed to perform specified logic functions. One type of PLD, the Field Programmable Gate Array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, Input/Output Blocks (IOBs), Configurable Logic Blocks (CLBs), dedicated Random Access Memory Blocks (BRAM), multipliers, Digital Signal Processing blocks (DSPs), processors, clock managers, Delay Lock Loops (DLLs), Multi-Gigabit Transceivers (MGTs) and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by Programmable Interconnect Points (PIPs). The programmable logic implements the logic of a user design using programmable elements that may include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and the programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data may be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to Input/Output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored off-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these PLDs, the functionality of the device is determined by the data bits used to configure the reconfigurable resources of the device. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Some PLDs, such as the Xilinx Virtex® FPGA, can be programmed to incorporate blocks with pre-designed functionalities, i.e., “cores”. A core can include a predetermined set of configuration bits that program the FPGA to perform one or more functions. Alternatively, a core can include source code or schematics that describe the logic and connectivity of a design. Typical cores can provide, but are not limited to, DSP functions, memories, storage elements, and math functions. Some cores include an optimally floor planned layout targeted to a specific family of FPGAs. Cores can also be parameterizable, i.e., allowing the user to enter parameters to activate or change certain core functionality.
PLDs often utilize global signal distribution resources that typically span the full width and/or the full height of the PLD. Such resources, often denoted as long line resources, are employed to propagate global signals to all portions of the PLD. The signals may include global clock signals that may be used to clock the sequential resources that are distributed across the entire device, such as the CLBs, BRAM, IOBs, and digital clock managers (DCMs). Other signals, such as the configuration data stream, may be propagated by the long line resources so that the memory cells that define the logic functions performed by the PLD may be programmed.
The long line resources, however, may add some form of distortion to the clock or data signals as they propagate from source to destination. Signal distortion may be caused by the particular transmission characteristics that are associated with the long line resources, such as distributed capacitive or inductive reactance, which may cause variations in propagation delay. Other causes of signal distortion may be introduced by combinatorial logic that may be associated with the long line resource, such as buffers or inverters. Such combinatorial logic may exhibit non-symmetric slew rates when propagating a logic low-to-high transition as compared to the propagation of a logic high-to-low transition. The ability to deterministically ascertain the characteristics of signal distortion within PLDs, therefore, continues to be desirable.